As the density of integrated circuits increases with decreasing size of component devices such as transistors, it becomes necessary to achieve precise arrangement of the devices on a semiconductor substrate with improved alignment accuracy simultaneously with obviating the generation of undue step height between plural wells in the devices during formation process.
Among previous methods for forming plural kinds of wells on a single semiconductor substrate, a couple of methods are here mentioned, one utilizing self-alignment techniques and the other using an alignment well.
The former method utilizing self-alignment techniques for forming plural kinds of wells on a single semiconductor substrate will be described herein below in reference to FIGS. 5A through 5F, which are cross-sectional views illustrating a twin-well semiconductor device during various stages in the manufacturing process according to the previous method utilizing self-alignment techniques.
In these drawings there are broadly divided into two regions from right to left an N well forming region 46 and P well forming region 48. In addition, the sentence blocks (a) through (f) in the following description will be referred to FIGS. 5A through 5F, respectively.
(a) A silicon oxide film 50 is formed on a silicon substrate 42 by the known thermal oxidation process;                a silicon nitride film 52 is subsequently formed on the silicon oxide film 50 by low pressure CVD (chemical vapor deposition);        a resist film 54 is formed on the silicon nitride film 52 having openings overlying the regions 46, 46, in which N wells are to be formed; and        the portions of the silicon nitride film 52 overlying the N well forming regions 46, 46 are removed.        
(b) With the use of thus patterned resist film 54 as a mask, phosphorus ions are implanted into the N well forming regions 46, 46 (as shown with “x” marks in FIG. 5B).
(c) Following the removal of the resist film 54, the surface of the structure is subjected to a thermal oxidation process using the silicon nitride film 52 as a mask for masking the P well forming region 48, whereby LOCOS (local oxidation of silicon) films 50a, 50a are formed on N well forming regions 46, 46. Thereafter, the structure is subjected to a thermal diffusion process to form N wells 56, 56.
(d) After removing the silicon nitride film 52 overlying the P well forming region 48, boron ions (as shown with “Δ” marks in FIG. 5D) are implanted into the P well forming region 48 using the LOCOS films 50a, 50a as masks.
(e) By subjecting the structure to a thermal diffusion process and subsequently removing the LOCOS oxide films 50a, 50a from the surface of silicon substrate 42, a twin-well structure is completed.
Another LOCOS oxide film 50b is formed on a predetermined region, and a gate oxide film 51 is formed on the surface of silicon substrate 42 covering the structure.
As described above, the implantation of impurities into the P well forming region 48 is performed in this alignment method after first forming N wells 56, 56, and then LOCOS oxide films 50a, 50a on the N well forming regions 46, 46 using the LOCOS oxide films 50a, 50a as masks, so that the impurities are prevented from the implantation into the P well forming region 48. As a result, this method is able to offer the advantage of reducing alignment mismatches (errors) between the N well 56 and P well 58.
In this method, however, a difference in the surface height may result between the N well 56 and P well 58 after the formation (FIG. 5E), which gives rise to a step height after the removal of the silicon oxide film 50 including LOCOS oxide film 50a. This step height in turn may cause the difficulty in focusing on a mask during aligning observation for forming gate electrodes and concomitant errors in finished measures.
In order to obviate the generation of such step height between the N well 56 and P well, another method has been disclosed to form the wells using an alignment mark (for example, Japanese Laid-Open Patent Application No. 6-45534).
The method for forming twin wells using an alignment mark will be described herein below referring to FIGS. 6A through 6E.
In these drawings there broadly divided into three regions from right to left are an alignment mark forming region 60, an N well forming region 62, and P well forming region 64. And, the sentence blocks (a) through (f) in the following description will be referred to FIGS. 6A through 6F, respectively.
(a) A silicon oxide film 66 is formed on a silicon substrate 42. Thereafter, a resist film 68 is formed with an opening overlying the alignment mark forming region 60 on the silicon oxide film 22.
By performing an anisotropic etching process on the alignment mark forming region 60 using the resist film 68 as a mask, an alignment mark 70 is formed.
(b) After removing the resist film 68, another resist film is formed having an opening overlying the N well forming region 62 on the silicon oxide film 66. Using this resist film as a mask, phosphorus ions are implanted into the N well forming region 62.
Subsequent to the removal of the resist film on the silicon oxide film 66, the structure is subjected to a thermal diffusion process to thereby form the N well 72.
(c) Still another resist film is formed having an opening overlying the P well forming region 64 on the silicon oxide film 66. Using this resist film as a mask, boron ions are implanted into the P well forming region 64.
Thereafter, the resist film is removed from the silicon oxide film 66, the structure is subjected to a thermal diffusion process, and the P well 74 is formed.
(d) After removing the silicon oxide film 66, another silicon oxide film 76 is formed on the entire surface of the structure on the silicon substrate 42, and a silicon nitride film 78 is formed on the silicon oxide film 76.
Thereafter, another resist film is formed on the silicon nitride film 78, having an opening overlying a LOCOS forming region 64.
An opening is then formed by selectively removing the portion of the silicon nitride film 78 overlying the LOCOS forming region using the resist film as a mask. The resist film is subsequently removed from the silicon nitride film 78.
(e) The surface of the structure is subjected to a thermal oxidation process using the silicon nitride film 7 as a mask, whereby a LOCOS oxide 80 is formed in the LOCOS forming region. Subsequent to the removal of the silicon nitride film 78, the semiconductor device with the twin-well structure is completed.
In the abovementioned method of forming twin wells using an alignment mark, the alignment mark 70 is first formed. And, with respect to thus formed alignment mark 70, the positioning of the N well 72, P well 74, and LOCOS oxide 80 is carried out.
In contrast to the method mentioned earlier utilizing self-alignment techniques in reference to FIGS. 6A through 6F, the present method using the alignment mark can be performed without forming the LOCOS film 50a on the N well forming region. Therefore, the difference in surface height (i.e., step height) is not generated between the N well 72 and P well 74, and no focusing error on the mask arises during the formation of gate electrodes.
In this method, however, photolithographic processes with respect to the alignment mark 70 are required each for implanting impurities into the N and P well forming regions. As a result, the number of times of aligning (positioning) increases and more alignment mismatches may arise accordingly.
As described above, the known methods for forming plural kinds of wells utilizing either self-alignment techniques or alignment mark each have encountered the difficulties in improving alignment accuracy simultaneously with obviating the generation of step height between the wells.
There is a need for an improved method for forming semiconductor devices which does not have the aforementioned disadvantages.